# Vivado TCL 命令参考：Block Design

> 来源: UG835 (v2018.3 / v2025.2)
> IP Integrator 子系统命令

## create_bd_design

创建 Block Design:
```tcl
create_bd_design "<name>"
```

## create_bd_cell

添加 IP 核到 BD:
```tcl
create_bd_cell -type ip -vlnv <vlnv> <cell_name>
create_bd_cell -type hier <cell_name>       # 创建层次模块
```

| 参数 | 说明 |
|------|------|
| `-type` | `ip` (IP核) / `hier` (层次) / `module` (RTL模块) |
| `-vlnv` | Vendor:Library:Name:Version |
| `<cell_name>` | 单元名称 |

常用 VLNV:
```
xilinx.com:ip:processing_system7:5.5      # ZYNQ PS
xilinx.com:ip:axi_dma:7.1                 # AXI DMA
xilinx.com:ip:aurora_8b10b:11.1            # Aurora 8B/10B
xilinx.com:ip:axi_interconnect:2.1         # AXI Interconnect
xilinx.com:ip:proc_sys_reset:5.0           # 复位模块
xilinx.com:ip:axi_gpio:2.0                # AXI GPIO
xilinx.com:ip:clk_wiz:6.0                 # 时钟向导
xilinx.com:ip:xlconcat:2.1                # 信号合并
xilinx.com:ip:xlconstant:1.1              # 常量
```

## 配置 IP 属性

```tcl
# 单个属性
set_property CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} [get_bd_cells ps_0]

# 批量属性（推荐）
set_property -dict [list \
    CONFIG.c_include_sg {1} \
    CONFIG.c_m_axi_mm2s_data_width {64} \
    CONFIG.c_mm2s_burst_size {256} \
] [get_bd_cells axi_dma_0]
```

## apply_bd_automation

自动化连接:
```tcl
# ZYNQ PS 自动化
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 \
    -config {make_external "FIXED_IO, DDR" apply_board_preset "1" \
             Master "Disable" Slave "Disable"} \
    [get_bd_cells processing_system7_0]

# AXI 互连自动化
apply_bd_automation -rule xilinx.com:bd_rule:axi4 \
    -config {Master "/processing_system7_0/M_AXI_GP0" Clk "Auto"} \
    [get_bd_intf_pins axi_dma_0/S_AXI_LITE]

# 时钟复位自动化
apply_bd_automation -rule xilinx.com:bd_rule:clkrst \
    -config {Clk "/processing_system7_0/FCLK_CLK0 (100 MHz)"}
```

## connect_bd_intf_net

连接 AXI 等接口:
```tcl
connect_bd_intf_net \
    [get_bd_intf_pins processing_system7_0/M_AXI_GP0] \
    [get_bd_intf_pins axi_interconnect_0/S00_AXI]
```

## connect_bd_net

连接普通信号:
```tcl
connect_bd_net \
    [get_bd_pins processing_system7_0/FCLK_CLK0] \
    [get_bd_pins axi_dma_0/s_axi_lite_aclk]
```

## assign_bd_address

自动分配地址:
```tcl
assign_bd_address
```

## validate_bd_design / save_bd_design

```tcl
validate_bd_design
save_bd_design
```

## make_wrapper

生成 HDL Wrapper:
```tcl
make_wrapper -files [get_files system.bd] -top
```

## make_bd_pins_external / make_bd_intf_pins_external

导出引脚到顶层:
```tcl
make_bd_pins_external [get_bd_pins aurora_0/GT_DIFF_REFCLK1]
make_bd_intf_pins_external [get_bd_intf_pins aurora_0/GT_SERIAL_TX]
```

## 典型 ZYNQ PS 配置属性

| 属性 | 说明 | 示例值 |
|------|------|--------|
| `CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ` | FCLK0 频率 | `100` |
| `CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ` | FCLK1 频率 | `200` |
| `CONFIG.PCW_EN_CLK1_PORT` | 启用 FCLK1 | `1` |
| `CONFIG.PCW_USE_M_AXI_GP0` | 启用 M_AXI_GP0 | `1` |
| `CONFIG.PCW_USE_M_AXI_GP1` | 启用 M_AXI_GP1 | `1` |
| `CONFIG.PCW_USE_S_AXI_HP0` | 启用 S_AXI_HP0 | `1` |
| `CONFIG.PCW_USE_S_AXI_HP1` | 启用 S_AXI_HP1 | `1` |
| `CONFIG.PCW_UART0_PERIPHERAL_ENABLE` | 启用 UART0 | `1` |
| `CONFIG.PCW_USE_FABRIC_INTERRUPT` | 启用 PL 中断 | `1` |
| `CONFIG.PCW_IRQ_F2P_INTR` | IRQ 输入 | `1` |
